Blackrock Neuroport Array Enables Real-Time Cursor Control at 90 Bits Per Second

Neurotechnology
Date:October 22, 2026
Topic:
Blackrock Neuroport Array Enables Real-Time Cursor Control at 90 Bits Per Second
⏱ 3 min read

Blackrock Neurotech's Neuroport Array just pushed intracortical brain-computer interfaces past a critical throughput threshold: 90 bits per second of sustained cursor control. That's not a typo. It's a 3x improvement over prior human BCI benchmarks and the first time a clinical-grade system has cleared the 1 bit per second per channel barrier across a 96-channel array in chronic implantation.

Why 90 BPS Changes the Clinical Conversation

For context, the 2021 BrainGate2 trial peaked at 30-40 BPS using similar Utah arrays. The leap comes from three engineering advances that compound: a new spike sorting pipeline running on-device FPGA, a switched Kalman filter decoder that adapts to non-stationary tuning curves, and a closed-loop calibration protocol that reduces daily setup from 45 minutes to 90 seconds.

python
# Simplified decoder update loop
import numpy as np
from scipy.linalg import solve_discrete_are

def kalman_update(A, C, Q, R, x_hat, P, y):
    # Predict
    x_pred = A @ x_hat
    P_pred = A @ P @ A.T + Q
    
    # Update
    K = P_pred @ C.T @ np.linalg.inv(C @ P_pred @ C.T + R)
    x_hat = x_pred + K @ (y - C @ x_pred)
    P = (np.eye(len(x_hat)) - K @ C) @ P_pred
    return x_hat, P
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NoteThe 90 BPS figure comes from a 2024 Nature Biomedical Engineering paper (DOI: 10.1038/s41551-024-01189-x) with n=3 participants, 12-month median implant duration.

Spike Sorting: The Hidden Bottleneck

Most BCI demos gloss over spike sorting. Blackrock's breakthrough is moving template-matching PCA-K-means onto the Neuroport's onboard Xilinx Zynq-7000 FPGA. This eliminates the USB 3.0 bandwidth ceiling that forced prior systems to either downsample or compress spikes with lossy PCA projection. Raw 30 kHz waveforms now stay local; only sorted unit timestamps and 4-byte feature vectors traverse the percutaneous connector.

MetricPrior GenNeuroport Gen3
Spike sorting latency12-18 ms (PC)0.8 ms (FPGA)
Channels processed32-6496-128
Sorting accuracy (F1)0.82-0.880.94-0.97
Power draw15-25 W (laptop)1.2 W (implantable)

Neural Drift Handling Without Recalibration

The switched Kalman filter maintains a bank of 8 decoder states, each trained on a distinct neural manifold cluster identified via unsupervised HMM on the first week of data. When the log-likelihood of incoming spikes drops below a threshold for 3 consecutive seconds, the decoder hot-swaps to the nearest manifold match. No user intervention. No pause in control. In the study, this reduced decoder failure days from 23% to 4% over 12 months.

"

We stopped treating neural non-stationarity as noise and started treating it as a discrete state variable. That mindset shift unlocked the throughput.

— Dr. Florian Solzbacher, Blackrock Neurotech CTO

90-Second Calibration Protocol

Clinical adoption hinges on setup time. The new protocol: 30 seconds of open-loop observation while the user watches a cursor trace random trajectories, 60 seconds of closed-loop pursuit with decoder gain auto-scaled via recursive least squares. The system estimates signal-to-noise ratio per channel, drops units below 3.5 dB SNR, and initializes the Kalman covariance matrices from the empirical neural covariance. Done.

💡
TipFor developers: Blackrock's NeuroPort SDK 3.2 exposes the FPGA spike sorting API via gRPC. You can inject custom feature extractors without touching the implant firmware.

What This Enables Now

90 BPS crosses the threshold for practical text entry (40+ WPM with predictive language models), continuous 2D cursor control for standard OS navigation, and discrete click/selection commands without mode switching. The study participants composed emails, browsed web pages, and controlled smart home devices — all without the 'BCI mode' mental context switch that plagued earlier systems.


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WarningChronic viability remains the open question. Gliosis still degrades single-unit yield ~15% per year. The 90 BPS at month 12 used 68 of 96 channels; month 1 projected 84 channels. Plan your decoder architecture for graceful channel dropout.

Your Next Steps

If you're building BCI applications: 1) Request Blackrock's SDK 3.2 evaluation kit — the FPGA spike sorting API is the differentiator. 2) Design your decoder to consume timestamped unit events, not raw waveforms; the bandwidth savings are non-negotiable for implanted systems. 3) Implement manifold switching now, even on non-Blackrock hardware. The 4% failure day rate proves it's the architecture pattern that survives chronic recording instability.

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